/******************************************************************************
* Copyright (c) 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

/*
 * This is a temporary file with all new regiter definitions.
 * TODO: Synchronize with xpm_regs.h and remove.
 */


/**
 * Register: APU
 */
#define APU_CLUSTER0_RVBARADDR0L			((u32)0xECC00040U)
#define APU_CLUSTER0_RVBARADDR1L			((u32)0xECC00048U)
#define APU_CLUSTER1_RVBARADDR0L			((u32)0xECD00040U)
#define APU_CLUSTER1_RVBARADDR1L			((u32)0xECD00048U)
#define APU_CLUSTER2_RVBARADDR0L			((u32)0xECE00040U)
#define APU_CLUSTER2_RVBARADDR1L			((u32)0xECE00048U)
#define APU_CLUSTER3_RVBARADDR0L			((u32)0xECF00040U)
#define APU_CLUSTER3_RVBARADDR1L			((u32)0xECF00048U)


/**
 * Register: APU_PCIL
 */

#define APU_PCIL_BASEADDR				((u32)0xECB10000U)

#define APU_PCIL_CORE_0_BASEADDR			( APU_PCIL_BASEADDR + 0x00000000U)
#define APU_PCIL_CORE_1_BASEADDR			( APU_PCIL_BASEADDR + 0x00000030U)
#define APU_PCIL_CORE_4_BASEADDR			( APU_PCIL_BASEADDR + 0x000000C0U)
#define APU_PCIL_CORE_5_BASEADDR			( APU_PCIL_BASEADDR + 0x000000F0U)
#define APU_PCIL_CORE_8_BASEADDR			( APU_PCIL_BASEADDR + 0x00000180U)
#define APU_PCIL_CORE_9_BASEADDR			( APU_PCIL_BASEADDR + 0x000001B0U)
#define APU_PCIL_CORE_12_BASEADDR			( APU_PCIL_BASEADDR + 0x00000240U)
#define APU_PCIL_CORE_13_BASEADDR			( APU_PCIL_BASEADDR + 0x00000270U)

#define APU_PCIL_CORE_0_PWRDWN				( APU_PCIL_BASEADDR + 0x00000000U)
#define APU_PCIL_CORE_1_PWRDWN				( APU_PCIL_BASEADDR + 0x00000030U)
#define APU_PCIL_CORE_4_PWRDWN				( APU_PCIL_BASEADDR + 0x000000C0U)
#define APU_PCIL_CORE_5_PWRDWN				( APU_PCIL_BASEADDR + 0x000000F0U)
#define APU_PCIL_CORE_8_PWRDWN				( APU_PCIL_BASEADDR + 0x00000180U)
#define APU_PCIL_CORE_9_PWRDWN				( APU_PCIL_BASEADDR + 0x000001B0U)
#define APU_PCIL_CORE_12_PWRDWN				( APU_PCIL_BASEADDR + 0x00000240U)
#define APU_PCIL_CORE_13_PWRDWN				( APU_PCIL_BASEADDR + 0x00000270U)

#define APU_PCIL_CORE_PWRDWN_MASK			(0x00000001U)
#define APU_PCIL_CORE_PSTATE_OFFSET			(0x00000008U)
#define APU_PCIL_CORE_PSTATE_MASK			(0x0000003FU)
#define APU_PCIL_CORE_PSTATE_VAL			(0x00000048U)
#define APU_PCIL_CORE_PREQ_OFFSET			(0x00000004U)
#define APU_PCIL_CORE_PREQ_MASK				(0x00000001U)
#define APU_PCIL_CORE_PACTIVE_OFFSET			(0x0000000CU)
#define APU_PCIL_CORE_PACCEPT_MASK			(0x01000000U)
#define APU_PCIL_CORE_IDS_POWER_OFFSET			((u32)0x0000001CU)
#define APU_PCIL_CORE_ISR_POWER_OFFSET			((u32)0x00000010U)
#define APU_PCIL_CORE_ISR_WAKE_OFFSET			((u32)0x00000020U)

#define APU_PCIL_CLUSTER_0_BASEADDR			( APU_PCIL_BASEADDR + 0x00008004U)
#define APU_PCIL_CLUSTER_1_BASEADDR			( APU_PCIL_BASEADDR + 0x00009004U)
#define APU_PCIL_CLUSTER_2_BASEADDR			( APU_PCIL_BASEADDR + 0x0000A004U)
#define APU_PCIL_CLUSTER_3_BASEADDR			( APU_PCIL_BASEADDR + 0x0000B004U)

#define APU_PCIL_CLUSTER_0_PACTIVE			( APU_PCIL_BASEADDR + 0x0000800CU)
#define APU_PCIL_CLUSTER_1_PACTIVE			( APU_PCIL_BASEADDR + 0x0000900CU)
#define APU_PCIL_CLUSTER_2_PACTIVE			( APU_PCIL_BASEADDR + 0x0000A00CU)
#define APU_PCIL_CLUSTER_3_PACTIVE			( APU_PCIL_BASEADDR + 0x0000B00CU )

#define APU_PCIL_CLUSTER_0_PSTATE			( APU_PCIL_BASEADDR + 0x00008008U )
#define APU_PCIL_CLUSTER_1_PSTATE			( APU_PCIL_BASEADDR + 0x00009008U )
#define APU_PCIL_CLUSTER_2_PSTATE			( APU_PCIL_BASEADDR + 0x0000A008U )
#define APU_PCIL_CLUSTER_3_PSTATE			( APU_PCIL_BASEADDR + 0x0000B008U )

#define APU_PCIL_CLUSTER_PREQ_OFFSET			(0x00000000U)
#define APU_PCIL_CLUSTER_PREQ_MASK			(0x00000001U)
#define APU_PCIL_CLUSTER_PSTATE_OFFSET			(0x00000004U)
#define APU_PCIL_CLUSTER_PSTATE_MASK			(0x0000007FU)
#define APU_PCIL_CLUSTER_PSTATE_VAL			(0x00000048U)
#define APU_PCIL_CLUSTER_PACTIVE_OFFSET			(0x00000008U)
#define APU_PCIL_CLUSTER_PACCEPT_MASK			(0x01000000U)
#define APU_PCIL_CLUSTER_ISR_POWER_OFFSET		((u32)0x0000000CU)
#define APU_PCIL_CLUSTER_ISR_WAKE_OFFSET		((u32)0x0000001CU)

#define PSX_APU_CLUSTER_RVBARADDR0L_MASK		(0xFFFFFFFCU)

/**
 * Register: RPU
 */
#define PSX_RPU_CLUSTER_A_CLUSTER_CFG			(0xEB580000U)
#define PSX_RPU_CLUSTER_B_CLUSTER_CFG			(0xEB590000U)
#define PSX_RPU_CLUSTER_C_CLUSTER_CFG			(0xEB5A0000U)
#define PSX_RPU_CLUSTER_D_CLUSTER_CFG			(0xEB5B0000U)
#define PSX_RPU_CLUSTER_E_CLUSTER_CFG			(0xEB5C0000U)

#define PSX_RPU_CLUSTER_A0_CORE0_CFG0			(0xEB588000U)
#define PSX_RPU_CLUSTER_A1_CORE1_CFG0			(0xEB58C000U)
#define PSX_RPU_CLUSTER_B0_CORE0_CFG0			(0xEB598000U)
#define PSX_RPU_CLUSTER_B1_CORE1_CFG0			(0xEB59C000U)
#define PSX_RPU_CLUSTER_C0_CORE0_CFG0			(0xEB5A8000U)
#define PSX_RPU_CLUSTER_C1_CORE1_CFG0			(0xEB5AC000U)
#define PSX_RPU_CLUSTER_D0_CORE0_CFG0			(0xEB5B8000U)
#define PSX_RPU_CLUSTER_D1_CORE1_CFG0			(0xEB5BC000U)
#define PSX_RPU_CLUSTER_E0_CORE0_CFG0			(0xEB5C8000U)
#define PSX_RPU_CLUSTER_E1_CORE1_CFG0			(0xEB588000U)

#define PSX_RPU_CLUSTER_A0_CORE_0_VECTABLE		(0xEB588008U)
#define PSX_RPU_CLUSTER_A1_CORE_1_VECTABLE		(0xEB58C008U)
#define PSX_RPU_CLUSTER_B0_CORE_0_VECTABLE		(0xEB598008U)
#define PSX_RPU_CLUSTER_B1_CORE_1_VECTABLE		(0xEB59C008U)
#define PSX_RPU_CLUSTER_C0_CORE_0_VECTABLE		(0xEB5A8008U)
#define PSX_RPU_CLUSTER_C1_CORE_1_VECTABLE		(0xEB5AC008U)
#define PSX_RPU_CLUSTER_D0_CORE_0_VECTABLE		(0xEB5B8008U)
#define PSX_RPU_CLUSTER_D1_CORE_1_VECTABLE		(0xEB5BC008U)
#define PSX_RPU_CLUSTER_E0_CORE_0_VECTABLE		(0xEB5C8008U)
#define PSX_RPU_CLUSTER_E1_CORE_1_VECTABLE		(0xEB5CC008U)

#define PSX_RPU_CLUSTER_CFG_SLSPLIT_MASK		(0x00000001U)

#define PSX_RPU_CLUSTER_CORE_VECTABLE_MASK		(0xFFFFFFE0U)

/**
 * Register: PMXC_GLOBAL
 */

#define PMXC_GLOBAL_BASEADDR					(0xF1110000U)

#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_APU0_CORE0_MASK		(0x00010000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_APU0_CORE1_MASK		(0x00020000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_APU1_CORE0_MASK		(0x00100000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_APU1_CORE1_MASK		(0x00200000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_APU2_CORE0_MASK		(0x01000000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_APU2_CORE1_MASK		(0x02000000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_APU3_CORE0_MASK		(0x10000000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_APU3_CORE1_MASK		(0x20000000U)

#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_RPUA_CORE0_MASK		(0x00000100U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_RPUA_CORE1_MASK		(0x00000200U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_RPUB_CORE0_MASK		(0x00000040U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_RPUB_CORE1_MASK		(0x00000080U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_RPUC_CORE0_MASK		(0x00000010U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_RPUC_CORE1_MASK		(0x00000020U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_RPUD_CORE0_MASK		(0x00000004U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_RPUD_CORE1_MASK		(0x00000008U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_RPUE_CORE0_MASK		(0x00000001U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE0_RPUE_CORE1_MASK		(0x00000002U)

#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B0_I0_MASK		(0x00010000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B0_I1_MASK		(0x00020000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B0_I2_MASK		(0x00040000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B0_I3_MASK		(0x00080000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B1_I0_MASK		(0x00100000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B1_I1_MASK		(0x00200000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B1_I2_MASK		(0x00400000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B1_I3_MASK		(0x00800000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B2_I0_MASK		(0x01000000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B2_I1_MASK		(0x02000000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B2_I2_MASK		(0x04000000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B2_I3_MASK		(0x08000000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B3_I0_MASK		(0x10000000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B3_I1_MASK		(0x20000000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B3_I2_MASK		(0x40000000U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_OCM_B3_I3_MASK		(0x80000000U)

#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_RPU_TCM_A0_MASK		(0x00000100U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_RPU_TCM_A1_MASK		(0x00000200U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_RPU_TCM_B0_MASK		(0x00000040U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_RPU_TCM_B1_MASK		(0x00000080U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_RPU_TCM_C0_MASK		(0x00000010U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_RPU_TCM_C1_MASK		(0x00000020U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_RPU_TCM_D0_MASK		(0x00000004U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_RPU_TCM_D1_MASK		(0x00000008U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_RPU_TCM_E0_MASK		(0x00000001U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE1_RPU_TCM_E1_MASK		(0x00000002U)

#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE2_GEM0_MASK		(0x00000001U)
#define PMXC_GLOBAL_PMC_MSTR_PWR_STATE2_GEM1_MASK		(0x00000002U)

#define PMXC_GLOBAL_PMC_AUX_PWR_STATE_0				( (PMXC_GLOBAL_BASEADDR) + (u32)0x00006100U )
#define PMXC_GLOBAL_PMC_AUX_PWR_STATE_1				( (PMXC_GLOBAL_BASEADDR) + (u32)0x00006104U )
#define PMXC_GLOBAL_PMC_AUX_PWR_STATE_2				( (PMXC_GLOBAL_BASEADDR) + (u32)0x00006108U )

/**
 * Register: PSXC_LPX_SLCR
 */

#define PSXC_LPX_SLCR_BASEADDR					(0xEB410000U)

#define PSXC_LPX_SLCR_WAKEUP0_IRQ_EN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050608U )
#define PSXC_LPX_SLCR_WAKEUP0_IRQ_DIS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005060CU )
#define PSXC_LPX_SLCR_WAKEUP0_IRQ_STATUS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050600U )
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_STATUS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050614U )
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_EN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005061CU )
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_DIS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050620U )

#define PSXC_LPX_SLCR_REQ_SWRST_INT_EN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00060008U )
#define PSXC_LPX_SLCR_REQ_SWRST_STATUS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00060000U )
#define PSXC_LPX_SLCR_REQ_PWRUP0_INT_EN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00060088U )
#define PSXC_LPX_SLCR_REQ_PWRUP0_INT_DIS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0006008CU )
#define PSXC_LPX_SLCR_REQ_PWRUP0_STATUS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00060080U )
#define PSXC_LPX_SLCR_REQ_PWRUP1_INT_EN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000600A8U )
#define PSXC_LPX_SLCR_REQ_PWRUP1_INT_DIS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000600ACU )
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000600A0U )
#define PSXC_LPX_SLCR_REQ_PWRUP2_INT_EN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000600C8U )
#define PSXC_LPX_SLCR_REQ_PWRUP2_INT_DIS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000600CCU )
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000600C0U )

#define PSXC_LPX_SLCR_REQ_PWRDWN0_STATUS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00060020U )
#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00060040U )
#define PSXC_LPX_SLCR_REQ_PWRDWN1_INT_EN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00060048U )
#define PSXC_LPX_SLCR_REQ_PWRDWN1_INT_DIS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0006004CU )
#define PSXC_LPX_SLCR_REQ_PWRDWN2_INT_EN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00060068U )
#define PSXC_LPX_SLCR_REQ_PWRDWN2_INT_DIS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0006006CU )
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00060060U )

#define PSXC_LPX_SLCR_POWER_DWN_IRQ_EN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050638U )
#define PSXC_LPX_SLCR_POWER_DWN_IRQ_DIS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005063CU )
#define PSXC_LPX_SLCR_POWER_DWN_IRQ_STATUS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050650U )

#define PSXC_LPX_SLCR_APU0_CORE0_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050000U )
#define PSXC_LPX_SLCR_APU0_CORE1_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050020U )
#define PSXC_LPX_SLCR_APU1_CORE0_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050040U )
#define PSXC_LPX_SLCR_APU1_CORE1_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050060U )
#define PSXC_LPX_SLCR_APU2_CORE0_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050080U )
#define PSXC_LPX_SLCR_APU2_CORE1_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000500A0U )
#define PSXC_LPX_SLCR_APU3_CORE0_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000500C0U )
#define PSXC_LPX_SLCR_APU3_CORE1_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000500E0U )

#define PSXC_LPX_SLCR_APU0_CORE0_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005000CU )
#define PSXC_LPX_SLCR_APU0_CORE1_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005002CU )
#define PSXC_LPX_SLCR_APU1_CORE0_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005004CU )
#define PSXC_LPX_SLCR_APU1_CORE1_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005006CU )
#define PSXC_LPX_SLCR_APU2_CORE0_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005008CU )
#define PSXC_LPX_SLCR_APU2_CORE1_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000500ACU )
#define PSXC_LPX_SLCR_APU3_CORE0_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000500CCU )
#define PSXC_LPX_SLCR_APU3_CORE1_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000500ECU )

#define PSXC_LPX_SLCR_WAKEUP0_IRQ_APU0_CORE0_MASK		(0x000000001U)
#define PSXC_LPX_SLCR_WAKEUP0_IRQ_APU0_CORE1_MASK		(0x000000002U)
#define PSXC_LPX_SLCR_WAKEUP0_IRQ_APU1_CORE0_MASK		(0x000000004U)
#define PSXC_LPX_SLCR_WAKEUP0_IRQ_APU1_CORE1_MASK		(0x000000008U)
#define PSXC_LPX_SLCR_WAKEUP0_IRQ_APU2_CORE0_MASK		(0x000000010U)
#define PSXC_LPX_SLCR_WAKEUP0_IRQ_APU2_CORE1_MASK		(0x000000020U)
#define PSXC_LPX_SLCR_WAKEUP0_IRQ_APU3_CORE0_MASK		(0x000000040U)
#define PSXC_LPX_SLCR_WAKEUP0_IRQ_APU3_CORE1_MASK		(0x000000080U)

#define PSXC_LPX_SLCR_RPU_PCIL_A0_BASEADDR			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010000U )
#define PSXC_LPX_SLCR_RPU_PCIL_A1_BASEADDR			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010100U )
#define PSXC_LPX_SLCR_RPU_PCIL_B0_BASEADDR			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011000U )
#define PSXC_LPX_SLCR_RPU_PCIL_B1_BASEADDR			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011100U )
#define PSXC_LPX_SLCR_RPU_PCIL_C0_BASEADDR			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111C4U )
#define PSXC_LPX_SLCR_RPU_PCIL_C1_BASEADDR			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111E4U )
#define PSXC_LPX_SLCR_RPU_PCIL_D0_BASEADDR			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011204U )
#define PSXC_LPX_SLCR_RPU_PCIL_D1_BASEADDR			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011224U )
#define PSXC_LPX_SLCR_RPU_PCIL_E0_BASEADDR			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011244U )
#define PSXC_LPX_SLCR_RPU_PCIL_E1_BASEADDR			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011264U )

#define PSXC_LPX_SLCR_RPU_PCIL_A0_ISR_OFFSET			((u32)0x00010000U)
#define PSXC_LPX_SLCR_RPU_PCIL_A1_ISR_OFFSET			((u32)0x00010100U)
#define PSXC_LPX_SLCR_RPU_PCIL_B0_ISR_OFFSET			((u32)0x00011000U)
#define PSXC_LPX_SLCR_RPU_PCIL_B1_ISR_OFFSET			((u32)0x00011100U)
#define PSXC_LPX_SLCR_RPU_PCIL_C0_ISR_OFFSET			((u32)0x000111C4U)
#define PSXC_LPX_SLCR_RPU_PCIL_C1_ISR_OFFSET			((u32)0x000111E4U)
#define PSXC_LPX_SLCR_RPU_PCIL_D0_ISR_OFFSET			((u32)0x00011204U)
#define PSXC_LPX_SLCR_RPU_PCIL_D1_ISR_OFFSET			((u32)0x00011224U)
#define PSXC_LPX_SLCR_RPU_PCIL_E0_ISR_OFFSET			((u32)0x00011244U)
#define PSXC_LPX_SLCR_RPU_PCIL_E1_ISR_OFFSET			((u32)0x00011264U)

#define PSXC_LPX_SLCR_WAKEUP1_IRQ_RPUA_CORE0_MASK		(0x00000001U)
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_RPUA_CORE1_MASK		(0x00000002U)
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_RPUB_CORE0_MASK		(0x00000004U)
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_RPUB_CORE1_MASK		(0x00000008U)
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_RPUC_CORE0_MASK		(0x00000010U)
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_RPUC_CORE1_MASK		(0x00000020U)
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_RPUD_CORE0_MASK		(0x00000040U)
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_RPUD_CORE1_MASK		(0x00000080U)
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_RPUE_CORE0_MASK		(0x00000100U)
#define PSXC_LPX_SLCR_WAKEUP1_IRQ_RPUE_CORE1_MASK		(0x00000200U)

#define PSXC_LPX_SLCR_RPU_CACHE_CNTRL_A0_MASK			(0x00000001U)
#define PSXC_LPX_SLCR_RPU_CACHE_CNTRL_A1_MASK			(0x00000002U)
#define PSXC_LPX_SLCR_RPU_CACHE_CNTRL_B0_MASK			(0x00000004U)
#define PSXC_LPX_SLCR_RPU_CACHE_CNTRL_B1_MASK			(0x00000008U)
#define PSXC_LPX_SLCR_RPU_CACHE_CNTRL_C0_MASK			(0x00000010U)
#define PSXC_LPX_SLCR_RPU_CACHE_CNTRL_C1_MASK			(0x00000020U)
#define PSXC_LPX_SLCR_RPU_CACHE_CNTRL_D0_MASK			(0x00000040U)
#define PSXC_LPX_SLCR_RPU_CACHE_CNTRL_D1_MASK			(0x00000080U)
#define PSXC_LPX_SLCR_RPU_CACHE_CNTRL_E0_MASK			(0x00000100U)
#define PSXC_LPX_SLCR_RPU_CACHE_CNTRL_E1_MASK			(0x00000200U)

#define PSXC_LPX_SLCR_RPU_PCIL_ISR_OFFSET			(0x00000000U)
#define PSXC_LPX_SLCR_RPU_PCIL_IDS_OFFSET			(0x0000000CU)
#define PSXC_LPX_SLCR_RPU_PCIL_IEN_OFFSET			(0x00000008U)
#define PSXC_LPX_SLCR_RPU_PCIL_PR_OFFSET			(0x00000080U)
#define PSXC_LPX_SLCR_RPU_PCIL_PS_OFFSET			(0x00000084U)
#define PSXC_LPX_SLCR_RPU_PCIL_PA_OFFSET			(0x00000088U)
#define PSXC_LPX_SLCR_RPU_PCIL_PWRDWN_OFFSET			(0x000000C0U)

#define LPD_SLCR_RPU_PCIL_A0_PS					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010084U )
#define LPD_SLCR_RPU_PCIL_A1_PS					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010184U )
#define LPD_SLCR_RPU_PCIL_B0_PS					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011084U )
#define LPD_SLCR_RPU_PCIL_B1_PS					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011184U )
#define LPD_SLCR_RPU_PCIL_C0_PS					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111D8U )
#define LPD_SLCR_RPU_PCIL_C1_PS					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111F8U )
#define LPD_SLCR_RPU_PCIL_D0_PS					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011218U )
#define LPD_SLCR_RPU_PCIL_D1_PS					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011238U )
#define LPD_SLCR_RPU_PCIL_E0_PS					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011258U )
#define LPD_SLCR_RPU_PCIL_E1_PS					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011278U )

#define LPD_SLCR_RPU_PCIL_A0_PR					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010080U )
#define LPD_SLCR_RPU_PCIL_A1_PR					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010180U )
#define LPD_SLCR_RPU_PCIL_B0_PR					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011080U )
#define LPD_SLCR_RPU_PCIL_B1_PR					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011180U )
#define LPD_SLCR_RPU_PCIL_C0_PR					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111D4U )
#define LPD_SLCR_RPU_PCIL_C1_PR					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111F4U )
#define LPD_SLCR_RPU_PCIL_D0_PR					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011214U )
#define LPD_SLCR_RPU_PCIL_D1_PR					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011234U )
#define LPD_SLCR_RPU_PCIL_E0_PR					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011254U )
#define LPD_SLCR_RPU_PCIL_E1_PR					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011274U )

#define LPD_SLCR_RPU_PCIL_A0_PA					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010088U )
#define LPD_SLCR_RPU_PCIL_A1_PA					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010188U )
#define LPD_SLCR_RPU_PCIL_B0_PA					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011088U )
#define LPD_SLCR_RPU_PCIL_B1_PA					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011188U )
#define LPD_SLCR_RPU_PCIL_C0_PA					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111DCU )
#define LPD_SLCR_RPU_PCIL_C1_PA					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111FCU )
#define LPD_SLCR_RPU_PCIL_D0_PA					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001121CU )
#define LPD_SLCR_RPU_PCIL_D1_PA					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001123CU )
#define LPD_SLCR_RPU_PCIL_E0_PA					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001125CU )
#define LPD_SLCR_RPU_PCIL_E1_PA					( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001127CU )

#define LPD_SLCR_RPU_PCIL_A0_ISR				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010000U )
#define LPD_SLCR_RPU_PCIL_A1_ISR				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010100U )
#define LPD_SLCR_RPU_PCIL_B0_ISR				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011000U )
#define LPD_SLCR_RPU_PCIL_B1_ISR				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011100U )
#define LPD_SLCR_RPU_PCIL_C0_ISR				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111C4U )
#define LPD_SLCR_RPU_PCIL_C1_ISR				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111E4U )
#define LPD_SLCR_RPU_PCIL_D0_ISR				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011204U )
#define LPD_SLCR_RPU_PCIL_D1_ISR				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011224U )
#define LPD_SLCR_RPU_PCIL_E0_ISR				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011244U )
#define LPD_SLCR_RPU_PCIL_E1_ISR				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011264U )

#define PSXC_LPX_SLCR_RPU_PCIL_A0_IEN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010008U )
#define PSXC_LPX_SLCR_RPU_PCIL_A1_IEN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00010108U )
#define PSXC_LPX_SLCR_RPU_PCIL_B0_IEN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011008U )
#define PSXC_LPX_SLCR_RPU_PCIL_B1_IEN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011108U )
#define PSXC_LPX_SLCR_RPU_PCIL_C0_IEN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111CCU )
#define PSXC_LPX_SLCR_RPU_PCIL_C1_IEN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111ECU )
#define PSXC_LPX_SLCR_RPU_PCIL_D0_IEN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001120CU )
#define PSXC_LPX_SLCR_RPU_PCIL_D1_IEN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001122CU )
#define PSXC_LPX_SLCR_RPU_PCIL_E0_IEN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001124CU )
#define PSXC_LPX_SLCR_RPU_PCIL_E1_IEN				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001126CU )

#define PSXC_LPX_SLCR_RPU_PCIL_A0_IDS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001000CU )
#define PSXC_LPX_SLCR_RPU_PCIL_A1_IDS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001010CU )
#define PSXC_LPX_SLCR_RPU_PCIL_B0_IDS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001100CU )
#define PSXC_LPX_SLCR_RPU_PCIL_B1_IDS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0001110CU )
#define PSXC_LPX_SLCR_RPU_PCIL_C0_IDS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111D0U )
#define PSXC_LPX_SLCR_RPU_PCIL_C1_IDS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111F0U )
#define PSXC_LPX_SLCR_RPU_PCIL_D0_IDS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011210U )
#define PSXC_LPX_SLCR_RPU_PCIL_D1_IDS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011230U )
#define PSXC_LPX_SLCR_RPU_PCIL_E0_IDS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011250U )
#define PSXC_LPX_SLCR_RPU_PCIL_E1_IDS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011270U )

#define PSXC_LPX_SLCR_RPU_PCIL_A0_PWRDWN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000100C0U )
#define PSXC_LPX_SLCR_RPU_PCIL_A1_PWRDWN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000101C0U )
#define PSXC_LPX_SLCR_RPU_PCIL_B0_PWRDWN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000110C0U )
#define PSXC_LPX_SLCR_RPU_PCIL_B1_PWRDWN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111C0U )
#define PSXC_LPX_SLCR_RPU_PCIL_C0_PWRDWN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000111E0U )
#define PSXC_LPX_SLCR_RPU_PCIL_C1_PWRDWN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011200U )
#define PSXC_LPX_SLCR_RPU_PCIL_D0_PWRDWN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011220U )
#define PSXC_LPX_SLCR_RPU_PCIL_D1_PWRDWN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011240U )
#define PSXC_LPX_SLCR_RPU_PCIL_E0_PWRDWN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011260U )
#define PSXC_LPX_SLCR_RPU_PCIL_E1_PWRDWN			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00011280U )

#define PSXC_LPX_SLCR_RPU_PCIL_PS_PSTATE_MASK			((u32)0x00000001U)
#define PSXC_LPX_SLCR_RPU_PCIL_PR_PREQ_MASK			((u32)0x00000001U)
#define LPD_SLCR_RPU_PCIL_PA_PACTIVE_MASK			((u32)0x00000003U)
#define PSXC_LPX_SLCR_RPU_PCIL_PA_PACCEPT_MASK			((u32)0x00000100U)
#define LPD_SLCR_RPU_PCIL_ISR_PACTIVE1_MASK			((u32)0x00000001U)
#define PSXC_LPX_SLCR_APU_CORE_PWR_CNTRL_STS_OFFSET		(0x0000000CU)
#define PSXC_LPX_SLCR_APU_CORE_PWR_CNTRL_PWRUP_GATES_MASK	((u32)0x00000001U)
#define PSXC_LPX_SLCR_APU_CORE_PWR_CNTRL_STS_ISOLATION_MASK	((u32)0x00000100U)

#define PSXC_LPX_SLCR_RPU_A0_POWER_DWN_MASK			(0x00010000U)
#define PSXC_LPX_SLCR_RPU_A1_POWER_DWN_MASK			(0x00020000U)
#define PSXC_LPX_SLCR_RPU_B0_POWER_DWN_MASK			(0x00040000U)
#define PSXC_LPX_SLCR_RPU_B1_POWER_DWN_MASK			(0x00080000U)
#define PSXC_LPX_SLCR_RPU_C0_POWER_DWN_MASK			(0x00100000U)
#define PSXC_LPX_SLCR_RPU_C1_POWER_DWN_MASK			(0x00200000U)
#define PSXC_LPX_SLCR_RPU_D0_POWER_DWN_MASK			(0x00400000U)
#define PSXC_LPX_SLCR_RPU_D1_POWER_DWN_MASK			(0x00800000U)
#define PSXC_LPX_SLCR_RPU_E0_POWER_DWN_MASK			(0x01000000U)
#define PSXC_LPX_SLCR_RPU_E1_POWER_DWN_MASK			(0x02000000U)

#define PSXC_LPX_SLCR_APU0_CORE0_PWRDWN_MASK			(0x00000001U)
#define PSXC_LPX_SLCR_APU0_CORE1_PWRDWN_MASK			(0x00000002U)
#define PSXC_LPX_SLCR_APU1_CORE0_PWRDWN_MASK			(0x00000004U)
#define PSXC_LPX_SLCR_APU1_CORE1_PWRDWN_MASK			(0x00000008U)
#define PSXC_LPX_SLCR_APU2_CORE0_PWRDWN_MASK			(0x00000010U)
#define PSXC_LPX_SLCR_APU2_CORE1_PWRDWN_MASK			(0x00000020U)
#define PSXC_LPX_SLCR_APU3_CORE0_PWRDWN_MASK			(0x00000040U)
#define PSXC_LPX_SLCR_APU3_CORE1_PWRDWN_MASK			(0x00000080U)

#define PSXC_LPX_SLCR_RPU0_CORE0_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050100U )
#define PSXC_LPX_SLCR_RPU0_CORE1_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050120U )
#define PSXC_LPX_SLCR_RPU1_CORE0_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050140U )
#define PSXC_LPX_SLCR_RPU1_CORE1_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050160U )
#define PSXC_LPX_SLCR_RPU2_CORE0_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050180U )
#define PSXC_LPX_SLCR_RPU2_CORE1_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000501A0U )
#define PSXC_LPX_SLCR_RPU3_CORE0_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000501C0U )
#define PSXC_LPX_SLCR_RPU3_CORE1_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000501E0U )
#define PSXC_LPX_SLCR_RPU4_CORE0_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050200U )
#define PSXC_LPX_SLCR_RPU4_CORE1_PWR_CNTRL_REG0			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050220U )

#define PSXC_LPX_SLCR_RPU0_CORE0_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005010CU )
#define PSXC_LPX_SLCR_RPU0_CORE1_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005012CU )
#define PSXC_LPX_SLCR_RPU1_CORE0_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005014CU )
#define PSXC_LPX_SLCR_RPU1_CORE1_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005016CU )
#define PSXC_LPX_SLCR_RPU2_CORE0_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005018CU )
#define PSXC_LPX_SLCR_RPU2_CORE1_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000501ACU )
#define PSXC_LPX_SLCR_RPU3_CORE0_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000501CCU )
#define PSXC_LPX_SLCR_RPU3_CORE1_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x000501ECU )
#define PSXC_LPX_SLCR_RPU4_CORE0_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005020CU )
#define PSXC_LPX_SLCR_RPU4_CORE1_PWR_CNTRL_STS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005022CU )

#define PSXC_LPX_SLCR_RPU_CORE_PWR_CNTRL_STS_ISOLATION_MASK	((u32)0x00000100U)
#define PSXC_LPX_SLCR_RPU_CORE_PWR_CNTRL_PWRUP_GATES_MASK	((u32)0x00000001U)
#define PSXC_LPX_SLCR_RPU_CACHE_PWR_CNTRL			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050400U )
#define PSXC_LPX_SLCR_RPU_CACHE_CE_CNTRL			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050404U )

#define PSXC_LPX_SLCR_OCM_CE_CNTRL				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050304U )
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B0_I0_MASK			((u32)0x00000001U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B0_I1_MASK			((u32)0x00000002U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B0_I2_MASK			((u32)0x00000004U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B0_I3_MASK			((u32)0x00000008U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B1_I0_MASK			((u32)0x00000100U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B1_I1_MASK			((u32)0x00000200U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B1_I2_MASK			((u32)0x00000400U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B1_I3_MASK			((u32)0x00000800U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B2_I0_MASK			((u32)0x00010000U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B2_I1_MASK			((u32)0x00020000U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B2_I2_MASK			((u32)0x00040000U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B2_I3_MASK			((u32)0x00080000U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B3_I0_MASK			((u32)0x01000000U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B3_I1_MASK			((u32)0x02000000U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B3_I2_MASK			((u32)0x04000000U)
#define PSXC_LPX_SLCR_OCM_CE_CNTRL_B3_I3_MASK			((u32)0x08000000U)

#define PSXC_LPX_SLCR_OCM_PWR_CNTRL				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050300U )
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B0_I0_MASK			((u32)0x00000001U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B0_I1_MASK			((u32)0x00000002U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B0_I2_MASK			((u32)0x00000004U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B0_I3_MASK			((u32)0x00000008U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B1_I0_MASK			((u32)0x00000100U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B1_I1_MASK			((u32)0x00000200U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B1_I2_MASK			((u32)0x00000400U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B1_I3_MASK			((u32)0x00000800U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B2_I0_MASK			((u32)0x00010000U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B2_I1_MASK			((u32)0x00020000U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B2_I2_MASK			((u32)0x00040000U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B2_I3_MASK			((u32)0x00080000U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B3_I0_MASK			((u32)0x01000000U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B3_I1_MASK			((u32)0x02000000U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B3_I2_MASK			((u32)0x04000000U)
#define PSXC_LPX_SLCR_OCM_PWR_CNTRL_B3_I3_MASK			((u32)0x08000000U)

#define PSXC_LPX_SLCR_OCM_PWR_STATUS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005030CU )
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B0_I0_MASK			((u32)0x00000001U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B0_I1_MASK			((u32)0x00000002U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B0_I2_MASK			((u32)0x00000004U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B0_I3_MASK			((u32)0x00000008U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B1_I0_MASK			((u32)0x00000100U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B1_I1_MASK			((u32)0x00000200U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B1_I2_MASK			((u32)0x00000400U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B1_I3_MASK			((u32)0x00000800U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B2_I0_MASK			((u32)0x00010000U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B2_I1_MASK			((u32)0x00020000U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B2_I2_MASK			((u32)0x00040000U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B2_I3_MASK			((u32)0x00080000U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B3_I0_MASK			((u32)0x01000000U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B3_I1_MASK			((u32)0x02000000U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B3_I2_MASK			((u32)0x04000000U)
#define PSXC_LPX_SLCR_OCM_PWR_STATUS_B3_I3_MASK			((u32)0x08000000U)

#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_TCM0A_MASK		((u32)0x00010000U)
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_TCM1A_MASK		((u32)0x00020000U)
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_TCM0B_MASK		((u32)0x00040000U)
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_TCM1B_MASK		((u32)0x00080000U)
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_TCM0C_MASK		((u32)0x00100000U)
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_TCM1C_MASK		((u32)0x00200000U)
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_TCM0D_MASK		((u32)0x00400000U)
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_TCM1D_MASK		((u32)0x00800000U)
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_TCM0E_MASK		((u32)0x01000000U)
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_TCM1E_MASK		((u32)0x02000000U)

#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_GEM0_MASK		((u32)0x10000000U)
#define PSXC_LPX_SLCR_REQ_PWRUP1_STATUS_GEM1_MASK		((u32)0x20000000U)

#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS_TCM0A_RET_MASK		((u32)0x00100000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS_TCM1A_RET_MASK		((u32)0x00200000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS_TCM0B_RET_MASK		((u32)0x00400000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS_TCM1B_RET_MASK		((u32)0x00800000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS_TCM0C_RET_MASK		((u32)0x01000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS_TCM1C_RET_MASK		((u32)0x02000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS_TCM0D_RET_MASK		((u32)0x04000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS_TCM1D_RET_MASK		((u32)0x08000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS_TCM0E_RET_MASK		((u32)0x10000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN1_STATUS_TCM1E_RET_MASK		((u32)0x20000000U)

#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND0_MASK	((u32)0x00000001U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND1_MASK	((u32)0x00000002U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND2_MASK	((u32)0x00000004U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND3_MASK	((u32)0x00000008U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND4_MASK	((u32)0x00000010U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND5_MASK	((u32)0x00000020U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND6_MASK	((u32)0x00000040U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND7_MASK	((u32)0x00000080U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND8_MASK	((u32)0x00000100U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND9_MASK	((u32)0x00000200U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND10_MASK	((u32)0x00000400U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND11_MASK	((u32)0x00000800U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND12_MASK	((u32)0x00001000U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND13_MASK	((u32)0x00002000U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND14_MASK	((u32)0x00004000U)
#define PSXC_LPX_SLCR_REQ_PWRUP2_STATUS_OCM_ISLAND15_MASK	((u32)0x00008000U)

#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND0_RET_MASK	((u32)0x00010000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND1_RET_MASK	((u32)0x00020000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND2_RET_MASK	((u32)0x00040000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND3_RET_MASK	((u32)0x00080000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND4_RET_MASK	((u32)0x00100000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND5_RET_MASK	((u32)0x00200000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND6_RET_MASK	((u32)0x00400000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND7_RET_MASK	((u32)0x00800000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND8_RET_MASK	((u32)0x01000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND9_RET_MASK	((u32)0x02000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND10_RET_MASK	((u32)0x04000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND11_RET_MASK	((u32)0x08000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND12_RET_MASK	((u32)0x10000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND13_RET_MASK	((u32)0x20000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND14_RET_MASK	((u32)0x40000000U)
#define PSXC_LPX_SLCR_REQ_PWRDWN2_STATUS_OCM_ISLAND15_RET_MASK	((u32)0x80000000U)

#define PSXC_LPX_SLCR_OCM_RET_CNTRL				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050308U )
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B0_I0_MASK			((u32)0x00000001U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B0_I1_MASK			((u32)0x00000002U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B0_I2_MASK			((u32)0x00000004U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B0_I3_MASK			((u32)0x00000008U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B1_I0_MASK			((u32)0x00000100U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B1_I1_MASK			((u32)0x00000200U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B1_I2_MASK			((u32)0x00000400U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B1_I3_MASK			((u32)0x00000800U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B2_I0_MASK			((u32)0x00010000U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B2_I1_MASK			((u32)0x00020000U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B2_I2_MASK			((u32)0x00040000U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B2_I3_MASK			((u32)0x00080000U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B3_I0_MASK			((u32)0x01000000U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B3_I1_MASK			((u32)0x02000000U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B3_I2_MASK			((u32)0x04000000U)
#define PSXC_LPX_SLCR_OCM_RET_CNTRL_B3_I3_MASK			((u32)0x08000000U)

#define PSXC_LPX_SLCR_RPU_TCM_RET_CNTRL				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050418U )
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050414U )
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL_TCMA0_MASK		((u32)0x00000001U)
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL_TCMA1_MASK		((u32)0x00000002U)
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL_TCMB0_MASK		((u32)0x00000004U)
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL_TCMB1_MASK		((u32)0x00000008U)
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL_TCMC0_MASK		((u32)0x00000010U)
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL_TCMC1_MASK		((u32)0x00000020U)
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL_TCMD0_MASK		((u32)0x00000040U)
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL_TCMD1_MASK		((u32)0x00000080U)
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL_TCME0_MASK		((u32)0x00000100U)
#define PSXC_LPX_SLCR_RPU_TCM_CE_CNTRL_TCME1_MASK		((u32)0x00000200U)

#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050410U )
#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL_TCMA0_MASK		((u32)0x00000001U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL_TCMA1_MASK		((u32)0x00000002U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL_TCMB0_MASK		((u32)0x00000004U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL_TCMB1_MASK		((u32)0x00000008U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL_TCMC0_MASK		((u32)0x00000010U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL_TCMC1_MASK		((u32)0x00000020U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL_TCMD0_MASK		((u32)0x00000040U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL_TCMD1_MASK		((u32)0x00000080U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL_TCME0_MASK		((u32)0x00000100U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_CNTRL_TCME1_MASK		((u32)0x00000200U)

#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x0005041CU )
#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS_TCMA0_MASK		((u32)0x00000001U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS_TCMA1_MASK		((u32)0x00000002U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS_TCMB0_MASK		((u32)0x00000004U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS_TCMB1_MASK		((u32)0x00000008U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS_TCMC0_MASK		((u32)0x00000010U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS_TCMC1_MASK		((u32)0x00000020U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS_TCMD0_MASK		((u32)0x00000040U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS_TCMD1_MASK		((u32)0x00000080U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS_TCME0_MASK		((u32)0x00000100U)
#define PSXC_LPX_SLCR_RPU_TCM_PWR_STATUS_TCME1_MASK		((u32)0x00000200U)

#define PSXC_LPX_SLCR_GEM_CE_CNTRL				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050424U )
#define PSXC_LPX_SLCR_GEM_CE_CNTRL_GEM0_MASK			((u32)0x00000001U)
#define PSXC_LPX_SLCR_GEM_CE_CNTRL_GEM1_MASK			((u32)0x00000002U)

#define PSXC_LPX_SLCR_GEM_PWR_CNTRL				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050420U )
#define PSXC_LPX_SLCR_GEM_PWR_CNTRL_GEM0_MASK			((u32)0x00000001U)
#define PSXC_LPX_SLCR_GEM_PWR_CNTRL_GEM1_MASK			((u32)0x00000100U)

#define PSXC_LPX_SLCR_GEM_PWR_STATUS				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050428U )
#define PSXC_LPX_SLCR_GEM_PWR_STATUS_GEM0_MASK			((u32)0x00000001U)
#define PSXC_LPX_SLCR_GEM_PWR_STATUS_GEM1_MASK			((u32)0x00000100U)

#define PSXC_LPX_SLCR_PWR_CTRL_STS_PRDY_SHIFT			(0U)
#define PSXC_LPX_SLCR_PWR_CTRL_STS_PRDY_WIDTH			((u32)4U)
#define PSXC_LPX_SLCR_PWR_CTRL_MAX_PWRUP_STAGES			PSXC_LPX_SLCR_PWR_CTRL_STS_PRDY_WIDTH

#define PSXC_LPX_SLCR_SCAN_CLEAR_TRIGGER			( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050910U )
#define PSXC_LPX_SLCR_MEM_CLEAR_TRIGGER				( (PSXC_LPX_SLCR_BASEADDR) + (u32)0x00050900U )

#define LPX_SLCR_RPU_PCIL_AB_PWRDWN_OFFSET			(0x000000C0U)
#define LPX_SLCR_RPU_PCIL_CDE_PWRDWN_OFFSET			(0x0000001CU)

/*
 * CRL
 */

#define PSX_CRL_BASEADDR					(0xEB5E0000U)

#define PSX_CRL_RST_RPU_A					( (PSX_CRL_BASEADDR) + (u32)0x00000310U )
#define PSX_CRL_RST_RPU_B					( (PSX_CRL_BASEADDR) + (u32)0x00000314U )
#define PSX_CRL_RST_RPU_C					( (PSX_CRL_BASEADDR) + (u32)0x00000318U )
#define PSX_CRL_RST_RPU_D					( (PSX_CRL_BASEADDR) + (u32)0x0000031CU )
#define PSX_CRL_RST_RPU_E					( (PSX_CRL_BASEADDR) + (u32)0x00000320U )

#define PSXC_CRL_RPU_CLK_CTRL					( (PSX_CRL_BASEADDR) + (u32)0x0000010CU )
#define PSXC_CRL_RPU_CLK_CTRL_CLKACT_MASK			(0x02000000U)

#define PSXC_CRL_RST_RPU_A_CORE0_RESET_MASK			(0x00000101U)
#define PSXC_CRL_RST_RPU_A_CORE1_RESET_MASK			(0x00000202U)
#define PSXC_CRL_RST_RPU_B_CORE0_RESET_MASK			(0x00000101U)
#define PSXC_CRL_RST_RPU_B_CORE1_RESET_MASK			(0x00000202U)
#define PSXC_CRL_RST_RPU_C_CORE0_RESET_MASK			(0x00000101U)
#define PSXC_CRL_RST_RPU_C_CORE1_RESET_MASK			(0x00000202U)
#define PSXC_CRL_RST_RPU_D_CORE0_RESET_MASK			(0x00000101U)
#define PSXC_CRL_RST_RPU_D_CORE1_RESET_MASK			(0x00000202U)
#define PSXC_CRL_RST_RPU_E_CORE0_RESET_MASK			(0x00000101U)
#define PSXC_CRL_RST_RPU_E_CORE1_RESET_MASK			(0x00000202U)

#define PSXC_CRL_GEM0_REF_CTRL					( (PSX_CRL_BASEADDR) + (u32)0x00000128U )
#define PSXC_CRL_GEM0_REF_CTRL_CLKACT_MASK			(0x02000000U)
#define PSXC_CRL_GEM1_REF_CTRL					( (PSX_CRL_BASEADDR) + (u32)0x0000012CU )
#define PSXC_CRL_GEM1_REF_CTRL_CLKACT_MASK			(0x02000000U)

#define PSXC_CRL_RST_GEM0					( (PSX_CRL_BASEADDR) + (u32)0x0000033CU )
#define PSXC_CRL_RST_GEM0_RESET_MASK				(0x00000001U)
#define PSXC_CRL_RST_GEM1					( (PSX_CRL_BASEADDR) + (u32)0x00000340U )
#define PSXC_CRL_RST_GEM1_RESET_MASK				(0x00000001U)


/*
 * CRF
 */

#define PSXC_CRF_BASEADDR					(0xEC200000U)

#define PSXC_CRF_ACPU0_CLK_CTRL					( (PSXC_CRF_BASEADDR) + (u32)0x0000010CU )
#define PSXC_CRF_ACPU1_CLK_CTRL					( (PSXC_CRF_BASEADDR) + (u32)0x00000110U )
#define PSXC_CRF_ACPU2_CLK_CTRL					( (PSXC_CRF_BASEADDR) + (u32)0x00000114U )
#define PSXC_CRF_ACPU3_CLK_CTRL					( (PSXC_CRF_BASEADDR) + (u32)0x00000118U )

#define PSXC_CRF_ACPU_CTRL_CLKACT_MASK				(0x02000000U)

#define PSXC_CRF_RST_APU0					( (PSXC_CRF_BASEADDR) + (u32)0x00000300U )
#define PSXC_CRF_RST_APU1					( (PSXC_CRF_BASEADDR) + (u32)0x00000304U )
#define PSXC_CRF_RST_APU2					( (PSXC_CRF_BASEADDR) + (u32)0x00000308U )
#define PSXC_CRF_RST_APU3					( (PSXC_CRF_BASEADDR) + (u32)0x0000030CU )

#define PSXC_CRF_RST_APU_CORE0_WARM_RST_MASK			(0x00000011U)
#define PSXC_CRF_RST_APU_CORE1_WARM_RST_MASK			(0x00000022U)
#define PSX_CRF_RST_APU_WARM_RST_MASK				(0x00000030U)
#define ACPU_CLUSTER_COLD_WARM_RST_MASK				((u32)0x00000300U)

/* TODO: Check these values are correct */
#define PSXC_LPX_SLCR_POWER_DWN_IRQ_DIS_RPU_SHIFT		(4U)
#define PSXC_GLOBAL_REG_PWR_CTRL1_IRQ_RPU_X_COREX_SHIFT		(4U)
